System Architecture

Overview

Chestnut uses a highly modular design consisting of five boards. Each board is connected across a rugged backplane to support its operation. The power board provides power to the digital, time, receive (Rx), and transmit (Tx) boards. The digital board provides an interface to control, configure, and send/receive data to/from the receive (Rx), transmit (Tx), and time boards. Clock distribution extends from the time board, which provides a very clean and stable clock distribution network. The default receive and transmit boards each comprise of four fully independent channels.

Figure 1: Overall system block diagram.

Power Distribution

Chestnut is powered by an internal 12V, 1000W, over current protected, DC power supply and accepts a standard IEC320 C13 120-240VAC computer power cable at the back of the unit. The power board distributes power to the backplane as shown in Figure 2.

Figure 2: Power board system block diagram

Digital board

The Chestnut digital board provides the digital processing that powers the Chestnut transceiver. It consists of an Intel Arria 10 FPGA, which includes an ARM Cortex-A9 processor on the FPGA (Figure 3). The ARM (HPS) portion of the board hosts the web server through which Chestnut can be configured, and a UART serial port, which is used to communicate with the Rx, Tx, and time modules. A separate high speed link allows serial data to be shared directly between the Rx and Tx boards and the FPGA fabric. This link also allows the data to be shared between the FPGA fabric and the 40Gbps or 100Gbps interface (accessed using the qSFP+ ports on the front of the device). Other peripherals, including USB devices, are accessed through the HPS portion of the FPGA.

Figure 3: Digital board system block diagram

Time Board

Clock distribution on the Chestnut SDR is fairly robust. The internal reference source is an oven-controlled crystal oscillator (OCXO) that provides a very stable (5ppb) and accurate 10MHz signal and may be tuned using the AD5624R nanoDAC. A single ended external reference clock may also be used, provided it meets the input swing requirements listed on the specifications page

The default clock configuration sees the 10MHz reference input frequency divided by two, and passed to the HMC6832 low noise, 2:8 differential, fanout clock buffer, where it is distributed to a LMK low jitter integrated PLL+VCO synthesizer. One of the buffered outputs is also accessible using the “Ref Out” port. The other output goes to an LMX2595 20-GHz wideband RF synthesizer on the Logen board.

The default configuration has been factory calibrated to provide a known (in-phase), deterministic relationship for all LMK04828 outputs. The leading edge of all outputs and internal VCOs have been synchronized at the reference inputs of all frequency synthesizers, converters, and transceivers.

Figure 4: Lily Time Board Architecture.

Receive Board Radio Chain

The Chestnut receive board consists of a radio front end terminating with the Texas Instruments ADS54J69 dual-channel, 16-bit, 500-MSPS Analog-to-Digital Converter. This architecture is duplicated four times, once for each channel.

Figure 5: Rx Board RF Channel

Transmit Board Radio Chain

The Chestnut transmit board consists of a radio front end originating with the Texas Instruments quad channel DAC38J84 digital-to-analog converter, as shown in the Figure below. The radio front end is duplicated four times. Channels A and B connect to one DAC, and channels C and D connect to another DAC.

Figure 6: Tx Board RF Channel

FPGA DSP Chains

A simplified illustration of the DSP chains for transmit and receive provides a broad outline of the FPGA processing from the SFP+ ports to the converters.

Figure 7: Simplified Tx DSP Chain

Figure 8: Simplified Rx DSP Chain