System Architecture

These specifications are intended to serve as a broad guide, with variable gain and attenuation stages set at midpoints. As variable stages are adjusted, performance generally improves.

Table 1: Input Parameters for Analysis

Input Parameters	Value	Units
Input Power	-55	dBm
Frequency	2000	MHz
Anaylsis B/W	150	MHz

Table 2: Rx and Tx Specifications

	Specifications	Value(lna)	Value (lna pa)	Units
Rx Chain Analysis	NF	4.8	3.1	dB
	SFDR	55	47	dB
	IMD	-113	-81	dB
	IIP3	-1.3	-17	dBm
	SNR	32	33	dB
	Rx Sensitivity	-86	-87	dBm
	Input P1dB	-28	-44	dBm
Tx Chain Analysis	Power Gain	-20 - 5		dBm
	SFDR		40 - 70	dB

Overview

Cyan benefits from a highly modular design consisting of several boards. Each board is connected across a rugged backplane to support its operation (Figure 1). The power board provides power to the various other boards. The digital board provides an interface to control, configure, and send/receive data to/from the receive (Rx), transmit (Tx) radio boards, and configures the time board. Clock distribution extends from the Time board, which provides a very clean and stable clock distribution network. The default product supports 8 fully independent transmit and receive chains, though this may be customized to support up to 16 transmit boards or 16 receive boards for receive or transmit only capabilities.

Figure 1: Overall system block diagram.

Power Distribution

Cyan uses an 12V, 1000W, over current protected, DC power supply and accepts a standard IEC320 C13 120-240VAC computer power cable at the rear of the unit. The power board distributes power to the backplane as shown in Figure 2.

Figure 2: Power board system block diagram

Digital board

The Cyan digital board provides the digital processing that configures the Cyan radio resources. It consists of an Intel Stratix 10 SOC FPGA, which includes an ARM Cortex-A53 quad-core processor on the FPGA (Figure 3). The ARM (HPS) portion of the board hosts various applications through which Cyan can be configured, along with the UART serial ports, which may be used to communicate with the various modules. A separate high speed link allows serial data to be shared directly between the Rx and Tx boards and the FPGA fabric. This link also allows the data to be shared between the FPGA fabric and the 40Gbps interface (accessed using the qSFP| ports on the front of the device). Other peripherals, including USB devices, are accessed through the HPS portion of the FPGA.

The Cyan HPS is connected to a 2GB DDR4 interface that supporting ECC. The FPGA fabric is connected to two 4GB DDR4 RAM banks.

Figure 3: Digital board system block diagram.

Time Board

Cyan time distribution is fairly robust. The internal reference source is an oven-controlled crystal oscillator (OCXO) that provides a very stable (5ppb) and accurate 10MHz signal that supports tuning using the AD5624R nanoDAC. A single ended external reference clock may also be used, provided it meets the input swing requirements listed on the specifications page

The default configuration has been factory calibrated to provide a known (in-phase), deterministic relationship for all LMK04828 outputs. The Leading edge of all outputs and internal VCOs have been synchronized at the reference inputs of all frequency synthesizers, converters, and transceivers.

Figure 4: Time Board Architecture.

Receive Board Radio Chain

The Cyan receive board consists of a radio front end terminating with the dual channel, 16bit, ADS54J60 1GSPS ADC at 1GSPS. It may also be used with the ADC32RF45, a dual channel, 12-bit, 3GSPS ADC. Each Rx radio board uses same architecture for each channel.

Figure 5: Rx Board RF Channel

Transmit Board Radio Chain

The Cyan transmit board consists of a radio front end originating with the AD9163 dual channel, 16bit, 1GSPS DAC. It is also possible to use the AD9162 DAC, which provides up to 2GHz of instantaneous bandwidth. This architecture is repeated for each transmit channel, as shown in Figure 6.

Figure 6: Tx Board RF Channel

FPGA DSP Chains

A simplified illustration of the DSP chains for transmit (Figure 7 ) and receive (Figure 8) provides a broad outline of the FPGA processing from the qSFP ports to the converters. The current architecture supports 40GBASE-R, but is upgradable to 100GBASE-R.

Figure 7: Simplified Tx DSP Chain.

Figure 8: Simplified Rx DSP Chain.