System Architecture

Overview

Calamine uses a modular design consisting of different circuit boards. Each board is connected using shielded, high speed cabling to support its operation. The power board provides power to the digital, time, and different receive (Rx) boards. The digital board provides an interface to control, configure, and send/receive data to/from the receive (Rx) and time boards. Clock distribution extends from the Time board, which provides a very clean and stable clock distribution network. The receive boards consist of different RF paths depending on tuning frequency and includes four fully independent channels with 8 SMA ports (4 for operation between DC and 20 GHz and 4 for operation between 20 and 40 GHz).

Figure 1: Overall system block diagram.

Power Distribution

Calamine is powered by an internal 12V, 200W, over current protected, DC power supply plugged into a standard IEC320 C13 120-240VAC computer power cable at the rear of the unit. The power board distributes power to the four daughter boards.

Figure 2: Power board system block diagram

Digital board

The Calamine digital board provides the digital processing that powers the Calamine receiver. It consists of an Altera Arria V ST SOC FPGA, which includes an ARM Cortex-A9 processor on the FPGA (Figure 3). The ARM (HPS) portion of the board hosts the web server through which Calamine can be configured, and a UART serial port, which is used to communicate with the Rx, and time modules. A separate high speed link allows serial data to be shared directly between the Rx boards and the FPGA fabric. This link also allows the data to be shared between the FPGA fabric and the 10Gbps interface (accessed using the SFP+ ports on the front of the device). Other peripherals, including USB devices, are accessed through the HPS portion of the FPGA.

Figure 3: Digital board system block diagram

Time Board

Clock distribution on the Calamine receiver is fairly robust. The internal reference source is an oven-controlled crystal oscillator (OCXO) that provides a very stable (5ppb) and accurate 10MHz signal and may be tuned using the AD5624R nanoDAC. A single ended external reference clock may also be used, provided it meets the input swing requirements listed on the specifications page

For all units (Figure 4), the default clock configuration sees the 10MHz reference input frequency divided by two, and passed to the CDCLVP1204 2:1 clock buffer, where it is distributed to the LMK low jitter integrated PLL+VCO synthesizers. One of the buffered outputs is also accessible using the “Ref Out” port. Note that the default configuration uses an internal 5MHz signal to support the default 325MHz sample rate, and to support phase coherent operation.

The LMK04828, by default, has a 10MHz input and uses the internal Phase Locked Loop (PLL1)to control a 100MHz low phase-noise VCXO. This locks the ultra low phase-noise 100MHz VCXO to the stability provided by the 10MHz input. The 100MHz VCXO output subsequently drives PLL2 of the first LMK04828. This provides a 322 MHz JESD204B (subclass 1) device clock and sysref clock to the converters and transceivers (ADC and FPGA).

A buffered copy of the 100MHZ VCXO output is also provided to a second LMK04828, through a second HMC 988. The buffered output drives the second PLL of the second LMK04828 and provides clocking to all frequency synthesizers for each front end channel. A buffered output of the analog reference signal is also provided (Ext.PLL) and a buffered copy of the original 100MHz reference signal is available on Ext. OSCout.

The default configuration has been factory calibrated to provide a known (in-phase), deterministic relationship for all LMK04828 outputs. The Leading edge of all outputs and internal VCOs have been synchronized at the reference inputs of all frequency synthesizers, converters, and transceivers.

Figure 4: Time Board Architecture.

Receive Board Radio Chain

The Calamine receive board consists of a radio front end terminating with the Texas Instruments dual channel ADC16DX370 analog-to-digital converter. This architecture is duplicated four times, once for each channel.

Figure 5: Rx Board RF Channel

FPGA DSP Chains

A simplified illustration of the DSP chains for receive provides a broad outline of the FPGA processing from the SFP+ ports to the converters.

Figure 6: Simplified Rx DSP Chain