Crimson Classic User Manual

Warning

This User Manual is deprecated

Preface

Crimson Classic is a high performance, wide band, high gain, direct conversion quadrature software defined radio transceiver and signal processing platform. It has four channels, each comprised of independent receive and transmit blocks, capable of processing up to 322MHz of instantaneous RF bandwidth from DC to 6GHz and synchronized using a JESD204B subclass 1 link to ensure deterministic latency. Data may be processed on the device itself (we have an Altera Arria V ST FPGA SoC on-board), or sent over low latency dual GB Ethernet links by connecting the integrated SFP+ headers to a compatible GBASE-R network device.

Crimson Classic is intended for advanced signal processing and data collection applications.

Congratulations!

Congratulations on your purchase of the Per Vices Crimson Classic Transceiver! This manual is intended to provide you with useful information regarding the safe operation and use of your new Transceiver. Although it may be updated from time to time, you’ll always be able to find the latest version on the Per Vices website.

In building Crimson Classic, we aimed to provide advanced capabilities at the lowest possible price. This product aims to provide a sophisticated platform capable of advanced RF Signal processing and includes a robust, and fully integrated, RF chain.

Our hope is that you will find Crimson Classic to be a useful and dependable companion in your engineering, development, and research efforts.

We welcome your feedback; please feel free to contact us at.

Obligatory Warnings

The following section contains important safety and regulatory information. Please pay attention to the following disclaimers, warnings, and cautions.

This device is intended for engineering, research, or science laboratory use only - it is not for open office or residential use. This device has not been tested or approved by any agency or approvals body for Electrical Safety, Electromagnetic Compatibility, or Telecommunications at the time of distribution! You use this device at your own risk.

Disclaimer

This product is provided «As Is». Per Vices is under no obligation to provide updates, upgrades, support, or maintenance of any kind. Per Vices specifically disclaims any and all warranties and guarantees, express, implied, or otherwise, arising with respect to the use of this product including, but not limited, to the warranty of merchantability, the warranty of fitness for a particular purpose, and any warranty of non-infringement of the intellectual property rights of any third party. Per Vices neither assumes nor authorizes any person to assume for it any other liability.

Use of this device is at your own risk. Per Vices shall not be liable for any damages, direct or indirect, incurred or arising from the use of this product. In no event will Per Vices be liable for loss of profits, loss of use, loss of data, business interruption, nor for punitive, incidental, consequential, or special damages of any kind, however caused, and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise), arising in any way out of the use of this product, even if advised of the possibility of such damages.

Every effort has been made to ensure that the device you receive is fully functional - each device is fully tested prior to shipping. Risk of damage or loss is transferred immediately upon delivery to you - we do not generally accept returns or refunds on successfully delivered packages. That being said, we do want to ensure your experience with Per Vices and Crimson Classic is a pleasant one and we encourage you to contact us at if you have any problems.

Specifications

Every effort has been made to test and measure the validity of this equipment. However, we cannot guarantee the accuracy of specifications, and they may change at any time.

Warnings
RISK OF ELECTRIC SHOCK Do not attempt to modify or touch the internals of this device. Ensure host computer is properly grounded during operation. Disconnect AC power during installing or removal.
HOT SURFACE This device may become very hot during operation; avoid contact. Ensure adequate ventilation and that unobstructed fan inlets.
LABORATORY USE ONLY This device has not been approved by any agency or approvals body for Electrical Safety, Electromagnetic Compatibility, or Telecommunications at the time of distribution. Research use only!
Attention
OBSERVE ESD PRECAUTIONS This device contains electrostatically sensitive components: it may be damaged by static discharges. Observe ESD precautions & proper grounding when handling, installing, or removing device.
RF TRANSMITTER This device is capable of RF transmission on bands or frequencies subject to regulatory oversight. Operators are responsible to ensure use of this device meets local regulatory and legal standards, as they may apply to you and the band of interest. This device is intended for test and measurement use only.

Specifications and Interfaces

Crimson Classic is a wide band, high gain, direct conversion quadrature transceiver.As Crimson Classic is capable of Digital Down/Up Conversion, superhet architectures can be implemented using Digital Down/Up Conversion on the FPGA. and signal processing platform. Using analogue and digital conversion, it is capable of processing signal bandwidths up to 322MHz from approximately DC to 6GHz. Crimson Classic is compatible with GNU Radio and includes source code for many of its drivers and peripherals.

Absolute Maximum Ratings

Stresses beyond those listed in the Absolute Ratings Table 1 may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and is, therefore, not recommended.

Table 1: Absolute Ratings

Exposure or sustained operation at absolute ratings may permanently damage Crimson Classic. Ensure fan intake vents (located on both sides of the device) are not blocked during operation.

Specification min max units notes
Ambient Operating Temperature 5 35 C measured at fan inlet
Ambient Operating Humidity 8 80 % non-condensing
Storage Temperature -35 70 C
Storage Humidity 20 95 % non-condensing
Input RF Power 15 dBm

Observed Performance

Crimson Classic is a very flexible radio and signal processing platform that supports high bandwidth communications over a wide tuning range. The hardware and signal processing capabilities may be configured to support a very wide variety of applications, each with their own figures of merit. It is, therefore, fairly challenging to provide uniform performance specifications across those different configurations.

To provide a general idea of what this product is capable of, table 2 provides some conservative figures of its out-of-box performance. Configuration of the product towards a specific application may see you exceed some of these figures at the expense of others. For more information, please do not hesitate to contact us.

Table 2: Observed Performance. These specifications reference observations taken during internal use and development. Calibration Measurements relative to 20^{o}C

Type Specification min nom max units
Temperature Opertaing Temperature 60 C
Common Radio RF Tuning (HMC833) 25 6000 MHz
Dyn. Range 70 dB
SFDR 65 dB
Receive Radio RF Input Power -20 dBm
Noise Figure 3.5 11 dB
Power Gain Low -4.5 65 dB
Power Gain High -15 55 dB
Group Delay (Radio Chain) Low 13.7 ns
Group Delay (Radio Chain) High 16 ns
ADC (Receive Converter) Independent Channels 4 -
ADC resolution 16 bits
ADC Sample Rate 322.265625 MSPS
Rx Sampling Bandwidth 322.265625 MHz
Latency (input to serial) 50 ns
Receive DSP and FPGA Specs Decimation (\frac{f_{s}}{n}) 1 256 -
Latency (FPGA DSP) 2 180 ns
Transmit Power Low - 20 dBm
Transmit Power High
Group Delay (radio chain) Low 4.3 ns
Group Delay (radio chain) High 8.9 ns
DAC (Transmit Converter) Tx Output Bandwidth 322.265625 MHz
DAC resolution 16 bits
DAC Sample Rate 322.265625 MSPS
Latency (serial to output) 50 655 804 ns
Transmit DSP and FPGA Specs Interpolation (n\cdot f_{s}) 1 256 -
Latency (FPGA DSP) 96 174 ns
Digital FPGA - Arria V ST SOC 5ASTMD3E3F31 -
On Board Processor Core ARM Cortex-A9 MP
LPDDR2 RAM 4 Gb
NAND Flash (x8) 4 Gb
Networking GBASE-R, Full Duplex each 8 Gbps
Default IP, SFP+ Port A . . .2 -
Default IP, SFP+ Port B . .11.2 -
Internal Reference ( MHz) Frequency Calibration -5 5 ppb

External Interfaces

Crimson Classic has a number of user accessible external interfaces through which the device can connect to external sources and sinks. Management functions are carried out over a web page hosted by the Crimson Classic transceiver and accessible using the management Ethernet port on the front face of the device. Data is sent over the Gbps SFP+ ports and receive and transmit antennas connect to the SMA connectors on the front of the device. Other peripherals ports provide access or the capability to improve functionality.

Operating System

Crimson Classic may be used with any operating system. After connecting the Crimson Classic Transceiver to an external network or computer using its dedicated Ethernet management port, you may configure the device using the provided web interface. It is also possible to SSH into the small Linux distribution running on the processor on-board.

Network Interface Card (NIC) Requirements

Crimson Classic uses a -gigabit Ethernet connection to quickly send and receive data. The Crimson Classic uses a GBASE-R PHY that interfaces with the SFP+ port using a single, .3125Gbps serial lane and a scrambled 64B/66B coding scheme. It is very important to ensure that network devices or interfaces intended to be used to connect to Crimson Classic support GBASE-R[margin: There is a significant difference between a GBASE-X interface (4 serial lanes specified to 3.125Gbps using 8b/ b coding), and the GBASE-R interface (1 serial lanes specified to .3125Gbps using 64b/66b coding) that Crimson Classic uses. Although both standards may expose the same mechanical SFP+ interface (and thereby allowing you to mechanically connect the two interfaces) the standards are fundamentally incompatible. Connecting Crimson Classic ( GBASE-R) to a network card that only supports GBASE-X or GBASE-T will not work. ]. The GBASE-R family includes GBASE-KR, GBASE-SR, GBASE-LR, and GBASE-ER interfaces.

Note that Crimson Classic also requires active cabling: using passive, direct connect, SFP+ cables is not supported. We recommend using active optical cabling (AOC) with integrated SFP+ transceivers. Alternatively, you may also choose to use a fibre cable and a compatible GBASE-R SFP+ optical transceiver module.

If you have any questions or concerns about NIC card requirements, please do not hesitate to contact us.

Mechanical

Crimson Classic conforms to a 1U form factor and 19-inch+ rack. A mechanical drawing in included in the Appendix.

RF Chain

Simulated RF chain performance (based on component specifications) yield the simulated performance indicated in table 3. As both the receive and transmission chains use variable stages, the figures were calculated using midpoint references for attenuation and gain stages. With proper tuning and calibration, you should expect better values. More information on the specific RF chain used may be found in the

Table 3: These specifications are intended to serve as a broad guide, with variable gain and attenuation stages set at midpoints. As variable stages are adjusted, performance generally improves.

Type Specification Value units
Input Parameters Input Power -55 dBm
Frequency 2000 MHz
Analysis B/W 150 MHz
Rx Chain Anaysis SFDR 40-55 dB
IMD -69 dB
IIP3 -23.5 dB
SNR 33.8 dB
Rx Sensitivity -85 dBm
Input P1dB -43 dBm
Tx Chain Analysis Power Gain dB
SFDR dB

System Architecture

Overview

Figure 1: Overall system block diagram.

Crimson Classic uses a highly modular design consisting of four boards. Each board is connected using shielded, high speed cabling, to support its operation (Figure 1). The digital board provides an interface to control, configure, and send/receive data to/from the receive (Rx), transmit (Tx), and time boards. Clock distribution extends from the Time board, which provides a very clean and stable clock distribution network. The default receive and transmit boards each comprise of four fully independent channels.

Digital board

The Crimson Classic digital board provides the digital processing that powers the Crimson Classic transceiver. It consists of a Altera Arria V ST SOC FPGA, which includes an ARM Cortex-A9 processor on the FPGA, and an Atmel ATxMega Microcontroller. The HPS portion of the board hosts the web server through which we can configure Crimson Classic, along with an Atmel ATxmega256A3 microcontroller, which is used to communicate with the Rx, Tx, and time module. A separate high speed link allows serial data to be shared directly between the Rx and Tx boards and the FPGA fabric. This link also allows the data to be shared between the FPGA fabric and the Gbps interface (accessed using the SFP+ ports on the front of the device). Other peripherals, including USB devices, are accessed through the HPS portion of the FPGA.

Time Board

Figure 3: Time Board Architecture

Clock distribution on the Crimson Classic transceiver is fairly robust (See Figure 3). Our internal reference source is an oven-controlled crystal oscillator (OCXO) that provides a very stable (5ppb) and accurate MHz signal. The reference clock is used as an input to the HMC 31MS8 Clock Generator with integer-N PLL to lock our external, ultra-low phase noise Crystec CVHD-950- 0.000 0MHz TCVXO to the long term stability of our OCXO. This improves output clock jitter and phase noise while preserving the stability and accuracy of our MHz reference. Ultimately, this leads to superior frequency stability, data converter signal-to-noise ratio (SNR), and digital PHY bit-error rates (BER).

This stable 0MHz output is fed through a 1:9 fan out buffer, whose primary output drives a Texas Instruments LMK04828B Clock Distribution chip. The remaining outputs are fed to the frequency synthesizers on the Rx and Tx boards, providing clean, 0MHz clocks for the digital board.

The outputs of the LMK04828 are used to generate the JESD204B device and system clocks required to ensure deterministic latency (subclass 1).

Receive Board Radio Chain

Figure 4: Rx Board RF Channel

The Crimson Classic receive board consists of a radio front end terminating with the Texas Instruments dual channel ADC16DX370 analog-to-digital converter, as shown in Figure 4. This architecture is duplicated four times, once for each channel.

Transmit Board Radio Chain

Figure 5: Tx Board RF Channel

The Crimson Classic transmit board consists of a radio front end originating with the Texas Instruments quad channel DAC38J84 digital-to-analog converter, as shown in Figure 5. The radio front end is duplicated four times. Channels A and B connect to one DAC, and channels C and D connect to another DAC.

Installation and Configuration

Installation and configuration comprises of four parts: physically installing the unit (attaching antennas, cables, power), configuring the host computer interfaces, building and installing the Per Vices libUHD library on the host computer, and testing the units. This is shown in Figure 6.

Figure 6: Crimson Classic Installation and Configuration

Physical Installation

Figure 7: Crimson Classic Installation

Physical installation comprises of five steps, as shown in Figure 7.

  1. Connecting the power plug.
  2. Connecting an RJ-45 cable from the Management port on Crimson Classic to the client computer.
  3. Connecting the GBASE-R cables to the host computer.
  4. Attaching the antennas to the Transmit and Receive ports (the Transmit port is labelled TXA - TXD and the Receive port is labelled RXA - RXD).
  5. Turning on the unit.

Default Crimson Classic Network Configuration

Figure 8: Host Configuration

Crimson Classic boasts three network ports. The order for basic configuration of these ports is laid out in Figure 8 The Management port is used to configure the device, while the two SFP+ ports are used to send data. Each SFP+ data port is connected to a specific antenna port. The default configuration has data on channels A and C sent over SFP+ A, and channels B and D sent over SFP+ B, as illustrated in Figure 9. The default network values are listed in Table 4, while the default recommended client networking configuration is in Table 5.

Figure 9: Default networking set up for Crimson Classic.

The destination IP addresses for receive ports may be modified using the web GUI. The default configuration sees information from Rx A sent to the destination IP address of

Table 4:

Default Crimson Classic Interface Addresses, including UDP destination ports for SFP+ headers.

SFP+ Interface Port A SFP+ Interface Port B Mgmt
Crimson Classic IP Address . . .2 . .11.2 192.168. .2
Radio Channels A C B D -
Destination IP (Rx) . . . . .11. -
Rx UDP Ports 42820, 42822 42821, 42823 -
Source IP (Tx) any any -
Tx UDP Ports 42824, 42826 42825,42827 -

Table 5: Host computer network configuration and used in the default configuration.

SFP+ Interface Port A SFP+ Interface Port B Mgmt
Host Address . . . . .11. 192.168. .4
Net Mask 255.255.255.0 255.255.255.0 255.255.255.0
Broadcast . . .255 . .11.255 192.168. .255
MTU 9000 9000 1500

Configuring Your IP Address to access the Management Site

In order to access the web interface, you will need to configure your IP address to share the same sub net (setting your machine to an IP of 192.168..4, and net mask of 255.255.255.0 should work), and then type the IP address into the browser; 192.168. .2. This should bring up the default connection screen for Crimson Classic (shown in Figure 10).

Figure 10: Home page of Crimson Classic Web UI, accessible through connection to the management port.

You can reconfigure the IP address, and host name, by clicking on the «Debug» tab of the home page.

You can also SSH into Crimson Classic with user name root. By default, there is no password set up.

Arch Linux

You can assign a static IP address in the console:

ip addr add XXX.XXX.XXX.XXX/YY broadcast ZZZ.ZZZ.ZZZ.ZZZ dev interface

For example:

ip addr add 192.168. .3 broadcast 192.168. .255 dev eth0

Debian/Ubuntu/Kubuntu

Log in as root and open a terminal

Make a backup of your /etc/network/interfaces file by typing the following in the console:

cp /etc/network/interfaces /etc/network/interfaces.backup

Then open vi by typing:

vi /etc/network/interfaces

Press «i» to enter into insert (editing) mode, and scroll down until you find your network interface card in the file. This usually starts with ethX for a wired network card (wireless cards generally start with wlanX or wifiX). This line generally holds a default value of «dhcp», which you need to replace with «static», after which you add the appropriate address, netmask, and network parameters. See table [ip-addr-repl-compare] for a specific example that illustrates the change that needs to be made. Once you have made the appropriate change, you can type «:wq» from within vi to save (write) your changes to the file and exit.

After making your changes, you may need to cycle your internet adapter. You may do this by typing the following command:

ifdown eth0; ifup eth0

Note: if you are remotely logged into the machine, it’s possible this may bring down the network adapter you are using. Therefore, ensure you have correctly identified your adapter prior to making this change.

Table 6: Sample line replacement within /etc/network/interfaces

old <…>
iface eth0 inet dhcp
<…>
new <…>
iface eth0 inet static
address 192.168..3 netmask 255.255.255.0 network 192.168..3
<…>

Windows (generic)

The following describes the generic method of changing your IP address using a Windows machine.

Go to Control Panel View Network Connections Right click on Local Area Connection and click on Properties Under the Networking tab select Internet Protocol Version 4 (TCP/IPv4) and click on Properties Select «Use the following IP address» Populate the IP address and subnet mask as described above Click OK

Configuring Your Data SFP+ IP Addresses

Assuming that the GBASE-R network card has already been installed into your host computer, the following instructions will guide you in properly configuring the SFP+ ports. From here, we will assume that the SFP+ port A is named XXXNXY. The IP address for this port will need to be configured to . . . .

Arch Linux

You can assign a static IP address in the console:

ip addr add XXX.XXX.XXX.XXX/YY broadcast ZZZ.ZZZ.ZZZ.ZZZ dev interface

For example, referencing Table [conf-default-hostconfig];

ip addr add  . . . /24 broadcast 255.255.255.0 dev XXXNXY

Type ip addr show into the console and the following output should appear to indicate that the link is up:

5: XXXNXY: mtu 9000 qdisc mq state UP group default qlen 00 link/ether NN:NN:NN:NN:NN:NN brd ff:ff:ff:ff:ff:ff

You can now ping the SFP+ Port A address …2 to ensure proper operation by typing the following into the console:

ping -I XXXNXY  . . .2

PING  . . .2 ( . . .2) from  . . .  XXXNXY: 56(84)
bytes of data.

64 bytes from  . . .2: icmp_seq=1 ttl=5 time=0.922 ms
64 bytes from  . . .2: icmp_seq=2 ttl=5 time=1.03 ms
...

In the event that . . .2 is not responding, you can type the following command into the console to check which IP address the port is linked to (shown as XX.XX.XX.XX):

ping -I XXXNXY -b 255.255.255.255

WARNING: pinging broadcast address

PING 255.255.255.255 (255.255.255.255) from  . . .  XXXNXY:
56(84) bytes of data.

64 bytes from XX.XX.XX.XX: icmp_seq=1 ttl=5 time=0.759 ms
64 bytes from XX.XX.XX.XX: icmp_seq=2 ttl=5 time=0.846 ms
...

To configure SFP+ Port B, repeat the above instructions but replace IP addresses as shown in Table [conf-default-hostconfig].

Debian/Ubuntu/Kubuntu

Log in as root and open a terminal

Make a backup of your /etc/network/interfaces file by typing the following in the console:

cp /etc/network/interfaces /etc/network/interfaces.backup

Then open vi by typing:

vi /etc/network/interfaces

Press «i» to enter into insert (editing) mode, and scroll down until you find your network interface card in the file. This line generally holds a default value of «dhcp», which you need to replace with «static», after which you add the appropriate address, netmask, and network parameters. See table [sfp-ip-addr-repl-compare] for a specific example that illustrates the change that needs to be made. Once you have made the appropriate change, you can type « :wq» from within vi to save (write) your changes to the file and exit.

After making your changes, you may need to cycle your internet adapter. You may do this by typing the following command:

ifdown XXXNXY; ifup XXXNXY

Note: if you are remotely logged into the machine, it’s possible this may bring down the network adapter you are using. Therefore, ensure you have correctly identified your adapter prior to making this change.

Table 6: Sample line replacement within /etc/network/interfaces

Old iface XXXNXY inet dhcp
New iface XXXNXY inet static
address 192.168.10.3 netmask 255.255.255.0
network 192.168.10.3

To configure SFP+ Port B, repeat the above instructions but replace IP addresses as shown in [conf-default-hostconfig].

Windows (generic)

Please refer to the previous Windows (generic) IP address configuration section.

Building the UHD Drivers

Figure 11: Compiling UHD Drivers

To fully realize the potential of Crimson Classic, you will need to build and install the UHD drivers. To do this, you will have to compile the Per Vices libUHD sources, as shown in [conf-flow-libUHD].

Obtaining the Per Vices UHD Sources

You can easily download the Per Vices UHD sources from github using the command line:

$ git clone https://github.com/pervices/uhd.git

Download the dependencies

Once you have downloaded the Per Vices UHD repository, you may want to confirm that you have all the dependencies required. Detailed instructions, including the dependencies, are available here

Note: In order to use Crimson Classic with UHD, you must download the Per Vices UHD version as it contains all the required modifications needed to support the Per Vices drivers.

Quick Install Instructions

We recommend that you carefully read the UHD build instructions. But, if you’re impatient, feeling lucky, and confident that you have all the dependencies, here is what you should be able to do:

download the dependencies

$ git clone https://github.com/pervices/uhd.git

enter the host directory

cd <uhd-repository-directory>/host
mkdir build
cd build
run cmake with the appropriate compile flags
cmake .. -DCMAKE_INSTALL_PREFIX=/usr/ \
    -DPYTHON_EXECUTABLE=/usr/bin/python2 \
    -DENABLE_EXAMPLES=OFF \
    -DENABLE_UTILS=ON \
    -DENABLE_TESTS=OFF \
    -DENABLE_E 0=ON
make -j4
make install

Use and Operation

This device is designed to be used and configured over a dedicated management port. The primary user interface can either be the a web UI, or you may directly configure the device over SSH.

Web UI

You can access the web interface by typing the IP address of the device in your browser. This directs you to a SCADA-like interface where you can easily visualize and configure the radio chain and DSP carried out on the device.

SSH and Command Line

You can also access and configure the device over SSH using command line parameters. This is primarly done using two programs; «uart-app» and «mem». The uart-app programs allow you to send commands over the UART bus to radio peripherals (like ADCs, DACs, or Amplifiers), and the mem application allows you to read and write to the memory space shared between the HPS and the FPGA.

Crimson Classic uart-app

Crimson Classic uses a number of MCUs, located on the Rx, Tx, Synthesizer, and Digital boards, to communicate and interface with various peripheral devices. This is done through a UART bus between the ARM Hard Processor System on the FPGA and the Atmel MCU on the digital board. The digital board has three other UART busses and forwards or processes requests through to the Rx, Tx, and Synthesizer board. You can directly poll and send commands to the MCU through the uart-app utility.

For example, to return a list of available commands on the synthesizer board, you might type:

uart-app ''help -v''

Board: DIG

Usage: [cmd] [-| ][arg1] [-| ][arg2]...

Commands:

  fpga Commands for controlling the FPGA:


  [r|rst] Resets the FPGA through the reset pin.

  dsp Configure the DSP features (FPGA/SW):


  [c|chan] Specify which channel a,b,c,d OR bit mask. MUST
    specify first.

  [s|stage] Enable the interpolator/decimator stage (1 - 5).
    SHOULD specify second.

  [h|chain] Specify which chain ADC(1), DAC(0). SHOULD specify
    third.

  [e|en] Enable(1) disable(0) the stage.

  [f|freq] Specify the frequency of the NCO.

  fwd Forward messages to the other boards:


  [b|board] Forward to RX(0), TX(1), SYNTH(2), echo(3).

  [m|msg] Forward message, max 25 chars.

  switch Switches the UART communication to another board:


  [t|tx] Switches to the TX board.

  [r|rx] Switches to the RX board.

  [s|synth] Switches to the Synth board.

  jesd Executes any JESD required commands:


  [s|sync] Re-sync all of the boards' sysref syncs.

  status Provides the status of the board:


  [f|fpga] Reads the status of the FPGA.

  [e|eth] Reads the status of the  G ethernet PHY.

  [r|ret] Reads the return value of the last function that was
    called.

  [p|pwr] Reads the current enabled power rails and pgood status.

  [i|i2c] Reads the status byte for the i2c register.

  test Executes test vectors:


  [f|fpga] Runs specified test vector of the FPGA.

  [e|eth] Runs specified test vector of the  G ethernet PHY.

  board Controls the board level functions. Sequential exec of
  arguments:


  [i|init] Rewrite all regs for entire board.

  [d|demo] Turn on outputs (per channel).

  [e|diag] Runs diagnostic on peripheral (per channel). Should
    print all registers.

  [m|mute] Turn off outputs (per channel).

  [r|reset] Power cycle peripherals and runs board init (per
    channel).

  [k|kill] Turn off peripherals. [p|panic] Turns everything off.

  [v|version] Prints out the software and hardware version.

  [l|led] Blinks the LED a specified number of times.

  [t|temp] Provides the temperature (0-1).

  [a|ram] Provides the amount of RAM left (bytes).

  boot Bootloader options:


  [e|enter] Enter the boot loader.

  exit Doesn't do anything, place holder:


  [-| ] No argument necessary.

  help Prints out the help menu for the board:


  [v|verbose] Prints out in verbose mode. 1 to enable.

Switching to a different board and typing the ‘’help -v’‘ operator provides you with board specific commands and configuration utilities for the respective peripherals.

Crimson Classic mem

If you choose to directly interface with the device over SSH, the mem tool is a helpful utility that allows you to read and write registers from the command line. The mem tool supports the following options:

mem [mr|mw|md|rr|rw|rd|rl] [address|reg_name|verbosity]
[value|length]

Where,

  mr memory read

  mw memory write

  md memory

  rr raw read

  rw raw write

  rd read double

  rl read long

  address the memory address in question

  reg_name the register memomic (as defined in the Crimson
  Classic Register Map).

  value hex value to write

  length length (in bytes) of a read

Sample Rates

The base sample rate for Crimson Classic Converters is 322.265625MSPS. All Rx channels and Tx channels A and B, sample at that rate. But due to FPGA limitations, the maximum supported sample rate on Tx channels C and D is 1/4 this value, or 80.56640625MSPS (322.265625MSPS/4). Depending on your use case, custom FPGA images may be developed that allow full rate sending over all Tx channels, however, this functionality is not included in the stock Crimson Classic image.

The default Crimson Classic FPGA image supports sample rates that are integer dividers of 322.265625MSPS. The possible native sample rates may be calculated as: 322.265625/N, where N = [2,65534].

It also includes a 4/5 resampler, though it is uncompensated. This allows for additional sample rates that are integer dividers of 257.8125MSPS (this number corresponds to (322.265625*4/5)MSPS), providing for an additional range of sample rates in the form of: 257.8125/N, where N = [1,65534]. Please note that RF performance may be degraded when using the resampler.

Device Data Format

Crimson Classic uses complex, signed, 32-bit integers to communicate data over the SFP+ ports.

Data Format

Data are transmitted in IQ pairs. Each IQ pair is 32 bits, with the I and Q components represented by two 16 bit signed integers. The specific format is represented in Table 8 . To read this data inside GNU radio, you can use a flow chart similar to that shown in Figure 12.

Table 8:

Bit Position 31:24 23:16 15:8 7:0
Representation Re[7:0] Re[15:8] Im[7:0] Im[15:8]

Figure 12: Sample gnuradio data sink, visualizing waterfall data.

Crimson Classic Register Map

The following pages detail the Crimson Classic register map. The register map is used to configure various parameters, including Gbps backhaul and JESD204B parameters between the FPGA and converter devices.

Updating Crimson Classic

This chapter discusses the procedure required to update the Crimson Classic transceiver firmware. Broadly speaking, Crimson Classic has two primary firmware sources: the FPGA firmware (containing the Linux file system and FPGA firmware), and the MCU firmware (the Atmel processor code used to control and configure the radio and time boards)More information on the architecture behind Crimson Classic may be found in [chap:System-Architecture]. . This chapter explains the procedure to update the MCU firmware, and configure the FPGA firmware to program the MCU.

MCU Firmware

The MCU code is responsible for controlling the various components on each radio board. When a command is issued from the digital board, the MCU interprets the command and configures or adjusts the various components on the board to the desired mode of operation.

The capability exists to update this code through the existing UART interface; the optimal update method takes advantage of the exposed SATA headers to directly update the Atmel Controller. The following provides the recommended procedure to update the MCU firmware.

Automatic MCU Update Pre-requisites

In order to automatically update from Crimson Classic, you require;

  1. Firmware binaries (eg; rx.hex, tx.hex)

The actual MCU firmware and binaries are available from Per Vices. If you are updating from the MCU, you only require the application binaries (rx.hex, tx.hex, synth.hex, dig.hex). Please contact us for more information.

  1. A client terminal with SSH and SCP installed.

Automatic MCU Update Procedure

  1. Copy the firmware binaries over to Crimson Classic, and place them within the /home/root/pv_mcu directory. If you are using the default configuration and wish to update all the MCUs, you can use the following scp invocation:

cd

scp {rx,tx,synth,dig}.hex root@192.168. .2:/home/root/pv_mcu If you have changed the default management IP address, then you will have to use that address.

  1. Once you have copied the MCU binaries, you must program them. This is done from within Crimson Classic. Accordingly, you need to SSH into the machine, then run the MCU update routine located in the /home/root/pv_mcu directory:

ssh root@192.168. .2

# cd /home/root/pv_mcu

# ./flash.sh allYou can update a specific board by specifying it; rx, tx, synth, dig.

  1. Once you have completed this process, restart Crimson Classic.

Manual MCU Update Pre-requisites

You require the following programs and items prior to updating the MCU firmware:

  1. avrdude

avrdude is a program that allows you to program Atmel MCUs. It is generally available in the package repositories of most Linux distributions. It is also available here . We presently use version 6.1.

  1. Firmware binaries (eg; rx.hex, rx-boot.hex)

The actual MCU firmware and binaries are available from Per Vices. Please contact us for more information. In order to fully program each board, you may require up to two binaries files per board. One is used to program the board boot-loader (identified by the -boot suffix), the other is an application binary (eg., rx.hex, tx.hex, dig.hex, or synth.hex).

  1. Programming dongle

A programming dongle is required to interface between the custom SATA header and an AVR-type programmer. You may build your own, or request one to be provided (on a limited basis). One SATA programming dongle is provided for the receive (Rx), transmit (Tx), and time (Synth) boards. A separate, mini-SAS type programmer is provided for the digital board.

Manual MCU Firmware Update Procedure

  1. Unplug the Crimson Classic chassis, and remove the cover.
  2. Locate the relevant board firmware header (see Figures [mcu-ProgHdr-rx] and [mcu-ProgHdr-dig]). (a) For the Receive (Rx), Transmit (Tx), or Time board (Synth), this is the SATA data header located beside the SATA power header. (b) For the Digital (Dig) board, the Rx port mini-SAS port doubles as the MCU programming header. You will need to carefully unplug the Rx Mini-SAS connector in order to insert the programming dongle.
  3. Mate the programming dongle with the appropriate board programming port.
  4. Program the application firmware, taking care to ensure you program the correct board with the correct firmware.

Your specific programmer and port may vary, requiring you to modify the port (-P) and controller (-c) options.

We use an avrispmkII compatible programmer over a usb connection, and want to program the rx.hex application firmware to the receive (Rx) board. We can use the following avrdude syntax;Remember to confirm that you are burning the correct application firmware file to the correct board!

avrdude -P usb -c avrispmkII -p x256a3u -B 8 \ -U application:w:rx.hex

We use a programmer controller (-c) that is avrispmkII compatible, uses a port (-P) usb connection, and sets a bit clock period in nanoseconds (-B) to 8. The part (-p) is an ATxmega256A3U, specified as x256a3u. We carry out a memory operation (-U) that writes the application binary rx.hex to memory.

  1. (Optional) Program the board boot-loader.

Your specific programmer and port may vary, requiring you to modify the port (-P) and controller (-c) options.

We use an avrispmkII compatible programmer over a usb connection, and want to program the rx-boot.hex boot loader to the receive (Rx) board. We can use the following avrdude syntax:Remember to confirm that you are burning the correct boot loader firmware file to the correct board!

avrdude -P usb -c avrispmkII -B 8 -e \ -p x256a3u -U boot:w:rx-boot.hex -U fuse2:w:0xBF:m

We use a programmer controller (-c) that is avrispmkII compatible, uses a port (-P) usb connection, and sets a bit clock period in nanoseconds (-B) to 8, after first performing a chip erase (-e). The part (-p) is an ATxmega256A3U, specified as x256a3u. We carry out a memory operation (-U) that writes the xboot-boot.hex file to the boot loader, and subsequently carries out another memory operation (-U) to set the fuses to (fuse2:w:0xBF:m).

  1. Congratulations! You have successfully updated the Crimson Classic MCU firmware.

Figure 13: The MCU programming header location on the Receive (Rx) board.

Figure 14: The MCU programming header location on the Transmit (Tx) board.

Figure 15: The MCU programming header location on the Time (Synth) board.

Figure 16: MCU programming header location on the Digital (Dig) board. It shares the same port as the mini-SAS cable going to the Rx board.

Figure 17: A sample debug adapter mated with an Atmel Programmer.

FPGA Firmware

The FPGA firmware used by Crimson Classic is stored on the provided Crimson Classic SD card and is loaded onto the FPGA during boot. This procedure describes how to replace or update the FPGA code stored on the SD card.

It is also possible to update the FPGA firmware using the command line, or directly over JTAG using a USB BlasterUpdating firmware using the USB Blaster is not recommended if you are also using the SoC, as it may adversely impact SoC operation. .

FPGA Update Pre-requisites

You require the following items prior to updating the FPGA firmware stored on the FPGA firmware:

  1. FPGA Binaries (soc_system.rbf)

This contains the FPGA firmware as a raw binary file (rbf) named soc_system.rbf. If you are compiling from source, or from within Quartus 2, you will have to convert the default output file (with an .sof extension - SRAM object file) to an appropriate RBF file. To do this, you must first compile the project. After compiling the project, open the Convert Programmer menu (File > Convert Programming Files) and use the settings shown in Figure [fpga-convfiles].

  1. Crimson Classic SD Card

The SD Card shipped with your Crimson Classic platform.

  1. Mini SD Card Reader All Crimson Classic transceivers ship with a USB card reader. Alternatively, you may use your own.
  2. A computer to copy over the SD Card. In order to copy over the SD Card, you will need a computer to copy the updated or generated FPGA firmware to the SD Card.

Figure 18: Quartus 2 IDE Convert Programming Files GUI. The settings illustrate the conversion of the default (.sof) file format to the desired raw binary file (.rbf), with a mode of Passive Parallel x16, and an output filename of soc_system.rbf.

FPGA Update Procedure

  1. If you are generating from your own Quartus Project, ensure that you have converted the newly generated source code to a Raw Binary File (see Figure [fpga-convfiles]).
  2. Confirm the file name is: soc_system.rbf
  3. Power down Crimson Classic, and remove the mini SD Card.
  4. Insert the SD Card into the provided USB mini-SD Card reader, and insert the assembly into a computer.
  5. Identify the partition containing the existing soc_system.rbf file.

The SD Card contains three partitions. Depending on your operating system, the number of viewable partitions may vary. Using a reasonable operating system, you should be able to view three partitions. For example:

sdX1 - partition 1- type b - W95 FAT32 partition (This contains the RBF file!)

sdX2 - partition 2 - type 83 - Linux ext3 partition (Contains SoC file system)

sdX2 - partition 3 - type a3 - UBOOT and boot loader (It’s best not to touch this)

  1. Once you identify the correct partition, replace the existing RBF file with the new one, and cleanly unmount the partitionYou must ensure you cleanly unmount the partition. You risk corrupting the firmware image (and possibly even Crimson Classic) if you simply remove the USB key without first unmounting (safely removing) the USB key! For added security, type «sync» to flush filesystem buffers prior to removing the SDCard.

  2. Remove the USB mini-SD Card adapter from your computer and pull out the mini-SD Card. Insert the bare SD card back into the Crimson Classic mini-SD Card receptacle.

  3. Congratulations! You should have successfully updated the Crimson Classic FPGA code.

So you’re swimming along, developing your own FPGA firmware when disaster strikes! There is a problem in your code. Despite countless hours simulating your code, you have discovered a bug. Worse, you aren’t sure exactly where it might lie, though, you suspect that the problem might come from that new code that Laura (from accounting) introduced. Before escalating the issue (or poisoning your relationship with your colleague), you want to debug the issue with Signal Tap. The following procedure indicates how to attach a USB Blaster to Crimson Classic.

FPGA Signal Tap Pre-requisites

You require the following items prior to updating the FPGA firmware stored on the FPGA firmware:

  1. Altera USB Blaster (or clone) with serial input.
  2. Crimson Classic Transceiver Platform

FPGA Signal Tap Attachment Procedure

  1. Remove the cover from Crimson Classic.
  2. Locate the Signal Tap header on the digital board (see Figure [fpga-signaltap]).

Default boards may not include a Signal Tap header, in which case you will need to solder on a dual row position header.

  1. Attach the Signal Tap header to the Jumpers.

  2. Congratulations! You have successfully attached a USB Blaster to Crimson Classic.

Figure 19: FPGA JTAG header location on digital board. You may use this jumper to attach a USB Blaster 2 device on to Crimson Classic, which enables you to use Signal Tap or carry out JTAG searches.

Mechanical Diagrams

Click the buttons below to download the relevant mechanical diagrams